The present invention relates to an ATM (asynchronous transfer mode) switching system.
In conventional ATM switching systems with a small switching capacity of about 2.4 Gbps, the dominant systems are of a simple input/output buffer type, as shown in FIG. 22, in which a high rate time division multiplex bus directly accommodates a low rate line interface usable by a user terminal.
The cell switching operation of an ATM (Asynchronous Transfer Mode) switching system with the conventional configuration will be described below. A class/line separator 112 identifies ATM cells flowed through the input line 110 by their destination output lines and service class types and then stores them to proper output line corresponding queues 111.
The rotation priority control section 108 controls such that a cell sending right is handed over in rotation between output line corresponding queues 111 belonging to the same service class. The interclass priority control section 109 controls competition for cell sending requests between different service classes in accordance with a predetermined priority control theory.
There are CBR (Constant Bit Rate), VBR (Variable Bit rate), ABR (Available Bit Rate), and UBR (Unspecified Bit Rate) as the service class.
The ATM cells, which are selected through a combination process of the rotation priority control section 108 and the interclass priority control section 109 and taken from the output line corresponding queue 111, are stored into the core switch queue 103 corresponding to the destination output line via the time division multiplex bus 104.
The core switch key 103 sequentially sends out ATM cells from the leading cell to the output line 101. The buffer occupancy computing section 105 in the core switch section 102 observes the queue length (buffer occupancy) of the core switch queue 103. The back pressure originating section 106 refers to the queue length information of the core switch key 103 holding the buffer occupancy computing section 105, and then originates the back pressure signal 113 specifying an output line in a congestion state to all input buffer module sections 110 when it detects that a core switch queue 103 in a congestion state exists because of the queue length exceeding a threshold value.
The back pressure receiving section 107 in the input buffer module section 110 specifies the output line originating a back pressure signal based on back pressure signal information received, and then reports the rotation priority control section 108 to inhibit sending cells from the output line corresponding queue 111 corresponding to the output line.
As described above, as traffic control between an input buffer and an output buffer in an ATM switching system with the conventional configuration, there has been only the simple back pressure control which originates a back pressure signal instructing to halt the outputting of a cell to a specific output line to all input buffer modules, in order to prevent the cell loss in the output buffer in the case of congestion of the specific output line.
In order to increase the switching capacity, the conventional method described above is made of the scheme of accommodating many low rate interfaces using higher rate time division multiplex bus. However, because the increasing number of input/output signals on the time division multiplex bus causes, for example, a shortage of the number of pins, it is difficult to realize the scheme in view of packaging on LSTS.
The conventional ATM switching system frequently originates back pressure signals to prevent a cell loss occurring in the output buffer because congestion occurs frequently because of simultaneous arrival of ATM cells to the same line from plural input lines.
Basically, the back pressure control has the effect of equalizing the throughput issued from each input line to the same output line. When the number of VCs (Virtual Channels) connected to the same output line is varied between input lines, the throughput evenness cannot be secured between VCs using the same output lines. Hence, in the conventional ATM switching system, the problem is that frequent occurrence of the back pressure signals causes the throughput evenness.